We are looking for someone with knowledge in functional verification using advance verification methodologies like UVM.
Has developed test strategy derived from RISC V specifications and comprehensive test suites in assembly language for extensions I, M, A, C etc..
Experience with RISC-V reference model for tests suite development using SPIKE RISC V ISA simulator.
Has developed assembly testcase for each or most of the extensions.
Familiarity with common RISC V architectures like RV32/64I, RV32/64E etc.
Following are the requirement list on a high level:
Familiarity with RISC-V Architecture
Ability to write and debug code in assembly languageC language programming skills Python programming skills
Familiarity with System Verilog, and ability to debug System Verilog simulations